1. Technical Field
The present invention relates in general to cache controllers in data processing systems and in particular to cache controllers which layer cache and architectural specific functions. Still more particularly, the present invention relates to layering cache and architectural specific functions within a controller to improve performance and simplify design.
2. Description of the Related Art
Data processing systems which utilize a level two (L2) cache typically include a cache controller for managing transactions affecting the cache. Such cache controllers are conventionally implemented on a functional level, as depicted in FIG. 3. For example, a cache controller 302 may include logic 304 for maintaining the cache directory, logic 306 for implementing a least recently used (LRU) replacement policy, logic for managing reload buffers 308, and logic for managing store-back buffers 310. In traditional implementations, the cache is generally very visible to these and other architectural functions typically required for cache controllers, with the result that cache controller designs are specific to a particular processors such as the PowerPC.TM., Alpha.TM., or the x86 family of processors.
The prior art approach imposes stringent and complex design requirements on the controller implementation. The maximum frequency obtainable is limited by the interlocks required. Testing and formal verification of the design may be frustrated by the complexity of the design. It would be desirable, therefore, to simplify the design of a cache controller to eliminate such complexities.